1. Field of the Invention
This invention relates to a manufacturing method of semiconductor, and more particularly, to self-aligned local interconnect and contact (SALIC) technology, which integrates a process of self-aligned and borderless contacts as well as a process of local interconnects.
2. Description of Related Art
When integration of elements in integrated circuits (IC) increases, a resistance of source/drain regions in the elements of metal oxide semiconductor (MOS) transistors simultaneously increases. As the resistance of the source/drain region is almost the same as the resistance of a channel of the MOS transistor, a process of self-aligned silicide (SALICIDE) is employed for reducing the sheet resistance of the source/drain regions in order to keep an integral of shallow junctions between the metal layer and the MOS transistor. The salicide process is currently applied in a manufacturing process of very large scale integration (VLSI) device.
Furthermore, a dual gate, such as a N.sup.+ /P.sup.+ poly dual gate, is employed in the element in deep submicron process when a demand for increasing the density of integrated circuits and decreasing the size of the elements is necessary. For a better performance, a tungsten silicide (WSi.sub.x) layer is used for covering the doped poly gate layer of elements, as the same time a poly silicide gate is formed by defining the tungsten suicide layer and the poly gate layer.
FIGS. 1A-1D are shown a conventional manufacturing process of self-aligned silicide. Referring to FIG. 1A, at first, there is a silicon substrate 10 which includes shallow trench isolation regions 11, a gate oxide layer 12a, and a poly gate layer 13a. The shallow trench isolation region 11 is formed by a plurality of steps. At first, shallow trenches are formed in the substrate 10. Then the shallow trenches are filled with, for example, silicon dioxide. Finally, the shallow trench isolation region 11 is formed by an anisotropic dry etching method. An active area 9 for a transistor element is sequentially formed beside every two shallow trench isolation regions 11.
Furthermore, the gate oxide layer 12a is made of, for example, silicon dioxide. The poly gate layer 13a is formed by, for example, a method of low pressure chemical vapor. The thickness of the poly gate layer 13a is about 2000 .ANG..about.3500 .ANG..
Referring to FIG. 1B, the poly gate layer 13a is covered by a tungsten silicide layer 14a. The tungsten suicide layer 14a can be formed by a process of low pressure chemical vapor deposition (LPCVD), in which the reaction is performed by, for example, a mixed gas of tungsten hexafluoride (WF.sub.6) and silane at a temperature of about 300.degree. C..about.400.degree. C. The thickness of the tungsten silicide layer 14a is about 400 .ANG..about.800 .ANG.. Next, a silicon nitride layer 15a is formed by depositing over the tungsten silicide layer 14a. The method of forming the silicon nitride layer 15a is, for example, a method of low pressure chemical vapor deposition.
Referring to FIG. 1C, a structure of gate electrode 13' is then formed above the substrate 10 by a conventional method of photolithography and etching, by which the gate oxide layer 12a, the poly gate layer 13a, the tungsten silicide layer 14a and the silicon nitride 15a are defined. The gate electrode 13' includes a gate oxide 12b, a poly gate layer 13b, a tungsten suicide layer 14b and a silicon nitride 15b.
Referring to FIG. 1D, a spacer 16 is formed around the sidewall of the gate electrode 13'. Then, the self-aligned silicide 17 is formed on a portion of the surface of the substrate 10. The self-aligned suicide 17 can be formed by steps of, at first, forming a titanium layer by sputtering over the sillicon 10. Next, the silicide 17 is formed in the interface of the titanium layer and the exposed parts of the substrate 10 by a method of, for example, a rapid thermal oxidation.
On the other hand, when the integration of the semiconductor device increases, the surface of the chip can not provide enough areas for interconnections inside the device. For catching up with increasing demands for interconnections inside, interconnections of more than two metal layers are currently employed in designs of integrated circuits, especially in complex IC products, e.g., a microprocessor. Even four or five metal layers are designed for interconnections of the elements in the microprocessor.
Referring to FIG.2A.about.2D, shown a conventional manufacturing process of local interconnects in local areas in the device. Referring to FIG. 2A, it shows a substrate 20, wherein the substrate 20 has a shallow trench isolation area 21 for defining the memory cells. Further, the substrate 20 is covered by a gate oxide layer 22, a first gate electrode 23 and a second gate electrode 24 formed above the gate oxide layer 22, and spacers 25 formed around the sidewalls of the first gate electrode 23 and the second gate electrode 24. The first gate electrode 23 and the second gate electrode 24 are made of, for example, polysilicon doped with impurities. The spacer 25 is made of, for example, silicon dioxide.
Referring to FIG. 2B, next, a process of forming self-aligned silicide (SALICIDE) is employed. Before employing the salicide process, the exposed portion of the gate oxide layer 22 is eliminated. The process includes steps of, for example, at first a metal layer is deposited over the first gate electrode 23, second gate electrode 23, and a gate oxide layer 22. The metal layer is, for example, a titanium layer deposited by magnetron DC sputtering. The thickness of the metal layer is preferably about 200.about.1000 .ANG.. Next, the titanium layer reacts with surface of the first gate electrode 23, the second gate electrode 24 and the exposed portion of the substrate 20 to produce the silicide 26 at a high temperature. The silicide is, for example, titanium silicide (TiSi.sub.2).
Referring to 2C, a titanium nitride layer 27a is deposited by reactive sputtering deposition over the substrate 20 to cover the first gate electrode 23, the second electrode 24, and the spacer 25. The method of reactive sputtering deposition uses the titanium as a metal target. Ions sputtered by bombard react with the nitrogen of the plasma in a circumstance filled with argon and nitrogen to produce titanium nitride (TiN). Then a photoresist layer 28 is formed over the substrate 20, wherein the photoresist layer 28 is defined to cover parts of the substrate 20. For example, referring to FIG. 2C, the portion of the titanium nitride layer 27a located on the surface of the first gate electrode 23 and half of the second gate electrode 24 is exposed.
Referring to FIG. 2D, the exposed titanium nitride 27a uncovered by the photoresist layer 28 is etched off and the residual titanium nitride layer 27b is formed. Next, in the following manufacturing process, the fore-end process of the local interconnect is performed by eliminating the photoresist layer 28. The back-end process can be easily performed by persons skilled in the art in order to complete the device.
Whereas, it is critical for a LOGIC technology to provide the self-aligned, borderless contacts, and local interconnects (LI) simultaneously. In the mean time, it has to be compatible with the LOGIC self-aligned titanium silicide(SALICIDE) and N+/P+ poly dual gate process modules. In the conventional manufacturing process, it has not been accomplished due to difficulties in integrating the salicide process and the LI into the logic salicide and N+/ P+ poly baseline process.